2.4GHz 可適性全數位頻率合成器

Please use this identifier to cite or link to this item: http://nchuir.lib.nchu.edu.tw/handle/309270000/116138

標題:	2.4GHz 可適性全數位頻率合成器 A 2.4GHz All-Digital Adaptive-Locked Frequency Synthesizer
作者:	黃名毅 Huang, Ming-Yi
Contributors:	黃崇禧;易昶霈 Chorng-Sii Hwang;Chang-Pei Yi 楊清淵 Ching-Yuan Yang 中興大學
關鍵字:	All-Digital Frequency Synthesizer 全數位頻率合成器
日期:	2012
Issue Date:	2012-09-11 10:29:17 (UTC+8)
Publisher:	電機工程學系所
摘要:	最近幾十年來，在製程的進步和電晶體尺寸縮小的趨勢，這可使電路設計上得到更高的操作頻率和更少的功率消耗，卻不利於類比電路設計；反之，這種趨勢更有利於數位電路設計，因此已有許多的類比電路改以數位方式實現，如:鎖相迴路和資料時脈回復電路。本論文將分成四個部分來做介紹。首先，第一部份則是探討一些基本的全數位鎖相迴路架構和其構成的單元。和通訊系統的應用頻帶與其規格。第二部分則介紹目前三個種類的鎖相迴路，類比式的鎖相迴路，數位式的鎖相迴路以及全數位式的鎖相迴路。鎖相迴路的基本理論以及設計，且會針對一些常用到的相位偵測器、電荷幫浦、壓控振盪器作分類說明。第三部分，我們提出了一個全數位鎖相迴路，這電路中包含了bang-bang相位偵測器、數位控制電路、數位壓控振盪器以及頻率偵測器。在這架構中，一個二位元型態的全數位鎖相迴路需要較長的頻率獲取時間，因為相位頻率偵測器的輸出僅為+1 和-1，故提出一個有效的減少頻率獲取時間的演算法，在全數位鎖相迴路中的數位控制振盪器對於電源雜訊有很大影響。最後，我們實現一個可應用在ISM 頻帶全數位式鎖相迴路，相較於傳統技術，此電路不但能快速鎖定，且具有低相位雜訊的優點。而此電路是以0.18 微米的互補式金氧半製程作模擬，操作在2.4GHz，相位雜訊約-135dBc/Hz，晶片面積為1.11.2mm2。 Over the last decades, the orientation of the fabrication process is to shrink the scaling of the transistor. Scaling down the transistor will have less power consumption and faster operation frequency to design circuits. However, it has extra drawbacks for analog circuits, but it is more suitable for digital circuits. Therefore, digital equivalent implementations of analog circuits are more popular, such as the phase-locked loop and the clock and data recovery. The thesis will be divided into four parts. First, the thesis describes an all-digital phase-locked loop for ISM frequency band in wireless communication. The second part of this thesis introduces the analog phase-locked loop (APLL), digital phase-locked loop (DLL) and all-digital phase-locked loop (ADPLL), introducing the fundamentals of the phase frequency detector, the charge pump, the loop filter and the voltage control oscillator. The third part primarily introduces an ADPLL. The ADPLL circuit contains a bang-bang type phase detector, a digital control circuit, a DCO and a frequency detector. The ADPLL needs long frequency acquisition time because the phase detector only has binary outputs, +1 and −1. The proposed algorithm can effectively reduce the frequency acquisition time. The supply noise toward the DCO has severely impact in ADPLL. In the last part, we realize an ADPLL for frequency synthesis. The frequency synthesizer is simulated in TSMC 0.18 CMOS technology. Its operation frequency is 2.4GHz, the total power is 40mW, the phase noise is about -135dBc/Hz at 1MHz offset, and the total area is 1.11.2mm2
Appears in Collections:	[依資料類型分類] 碩博士論文

Files in This Item:

File	Size	Format
index.html	0Kb	HTML	882	View/Open

Loading...

學術資源

著作權聲明