English  |  正體中文  |  简体中文  |  Items with full text/Total items : 43312/67235
Visitors : 2078983      Online Users : 32
RC Version 5.0 © Powered By DSPACE, MIT. Enhanced by NTU/NCHU Library IR team.

Please use this identifier to cite or link to this item: http://nchuir.lib.nchu.edu.tw/handle/309270000/116715

標題: 2.4GHz CMOS 鎖相迴路
2.4GHz CMOS Phase-Locked Loop
作者: 賴勝坤
Lai, Sheng -Kun
Contributors: 張振豪
Robert C.Chang
國立中興大學
關鍵字: 2.4GHz phase-locked loop;phase/frequency detector;charge-pump;low-pass filter;voltage-controlled oscillator;frequency divider
2.4GHz鎖相迴路;相位頻率檢知器;電荷幫浦;低通濾波器;壓控振盪器;除頻器
日期: 2003
Issue Date: 2012-09-11 10:36:31 (UTC+8)
Publisher: 電機工程學系
摘要: 本篇論文研究一個2.4GHz鎖相迴路,它包含著相位頻率檢知器(PFD)、電荷幫浦(Charge pump),低通濾波器(LPF)、壓控振盪器(VCO)、除頻器(Frequency Divider),這一個鎖相迴路可以用在無線通信系統,提供內部振盪頻率。
所設計鎖相迴路,其相位頻率檢知器,是用動態邏輯閘組成具有無dead zone的特性,可偵測外部號參考信號和除頻後的信號,當兩個信號比較相位差之後,相位頻率檢知器可以產生足夠寬度的up或down脈衝信號,供給電荷幫浦產生控制電壓,調整壓控振盪器的頻率。正回授CMOS 電荷幫浦,以對稱的電路來設計,具有正回授可增加交換速度的電荷幫浦,正回授及電流的再利用是被用來加快交換速度和低功率消耗,電荷幫浦可將偵測出來的相位差轉換成相對的電壓差,用來調變電壓控制壓控振盪器的振盪頻率。低通濾波器是用二階RC電路組成,用途在濾掉電荷幫浦所輸出的高頻成分。壓控振盪器是採用環形振盪器架構,由CMOS差動對組成delaycell,接受控制信路號調變delaycell的延遲時間,以調變輸出頻率,它的振盪頻率範圍是在1.75GHz~2.6GHz。除頻器是用到比例邏輯技術的TSPC動態正反器,達到快速除頻的要求。
整個2.4GHz頻率合成器系統的電源是2.8V,當控制電壓到1.82V時即可鎖住頻率為2.4GHz,鎖住時間為8μs,消耗功率為44.7mW,使用TSMC 0.35μm CMOS 1P4M 的製程技術來模擬與製作,晶片面積為221μm×71μm(不含R、C及IO Pad)。
In this thesis, a 2.4GHz CMOS phase-locked loop is designed,it is composed of a phase/frequency detector(PFD),a charge-pump(CP),a low-pass filter(LF),a voltage-controlled oscillator(VCO)and a frequency divider(FD).This frequency synthesizer can be employed in the wireless communication system to provide the internal oscillation frequency.
In the proposed phase-locked loop,the phase/frequency detector is made up of dynamic logic gates and without dead zone.The PFD can detect the phase and frequency error of the reference frequency and the divider output.After the two signals are compared,in the PFD, enough width of the up or down impulse signal is produced and sent to the CP,which produces a controlled voltage to adjust the frequency of the VCO.The positive feedback CMOS CP is designed by the symmetrical circuit,the CP with positive feedback can increase charging speed,and reuse of current can reduce power consumption.The CP transforms the phase and frequency error into a relative voltage difference to change the frequency of the VCO.The function of the second-order LF is composed of R and C and is to filter the high frequency component of the output signal of the CP.The VCO employs the ring-oscillator structure.The delay-cell consists of CMOS differential-pair and changes the delay time by the control voltage,to adjust the frequency of the VCO.The frequency of the VCO is 1.75GHz ~2.6GHz.The FD employs TSPC dynamic D flip-flop with ratio logic technique,to quickly achieve the request of the frequency dividing.
The supply voltage of the 2.4GHz CMOS phase-locked loop is 2.8V.The locking frequency is 2.4GHz when the controlled voltage is 1.82V.The locking time is 8μs,and power consumption is 44.7mW.This phase-locked loop is simulated and implemented by TSMC 0.35 μm CMOS 1P4M technology.The chip area is 221μm ×71μm(not including R、C and IO Pads).
Appears in Collections:[依資料類型分類] 碩博士論文

Files in This Item:

There are no files associated with this item.



 


學術資源

著作權聲明

本網站為收錄中興大學學術著作及學術產出,已積極向著作權人取得全文授權,並盡力防止侵害著作權人之權益。如仍發現本網站之數位內容有侵害著作權人權益情事者,請權利人通知本網站維護人員,將盡速為您處理。

本網站之數位內容為國立中興大學所收錄之機構典藏,無償提供學術研究與公眾教育等公益性使用。

聯絡網站維護人員:wyhuang@nchu.edu.tw,04-22840290 # 412。

DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU/NCHU Library IR team Copyright ©   - Feedback