English  |  正體中文  |  简体中文  |  Items with full text/Total items : 43312/67235
Visitors : 2106649      Online Users : 2
RC Version 5.0 © Powered By DSPACE, MIT. Enhanced by NTU/NCHU Library IR team.
National Chung Hsing University Institutional Repository - NCHUIR > 工學院 > 電機工程學系所 > 依資料類型分類 > 期刊論文 >  A 1.25-Gb/s burst-mode half-rate clock and data recovery circuit using realigned oscillation

Please use this identifier to cite or link to this item: http://nchuir.lib.nchu.edu.tw/handle/309270000/134894

標題: A 1.25-Gb/s burst-mode half-rate clock and data recovery circuit using realigned oscillation
作者: Yang, C.Y.;Lin, J.M.
楊清淵
關鍵字: burst-mode CDR;clock recovery;phase-locked loop;realigned oscillation;phase-noise;cmos
日期: 2007
Issue Date: 2012-12-14 11:12:00 (UTC+8)
關連: Ieice Transactions on Electronics, Volume E90C, Issue 1, Page(s) 196-200.
摘要: In this letter, a 1.25-Gb/s 0.18-mu m CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4 x 1.4 mm(2), and power consumption is 32 mW under a 1.8-V supply voltage.
Relation: Ieice Transactions on Electronics
Appears in Collections:[依教師分類] 楊清淵
[依資料類型分類] 期刊論文

loading Web of Knowledge data....

Files in This Item:

File SizeFormat
index.html0KbHTML499View/Open


 


學術資源

著作權聲明

本網站為收錄中興大學學術著作及學術產出,已積極向著作權人取得全文授權,並盡力防止侵害著作權人之權益。如仍發現本網站之數位內容有侵害著作權人權益情事者,請權利人通知本網站維護人員,將盡速為您處理。

本網站之數位內容為國立中興大學所收錄之機構典藏,無償提供學術研究與公眾教育等公益性使用。

聯絡網站維護人員:wyhuang@nchu.edu.tw,04-22840290 # 412。

DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU/NCHU Library IR team Copyright ©   - Feedback