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National Chung Hsing University Institutional Repository - NCHUIR > 工學院 > 光電工程研究所 > 依資料類型分類 > 碩博士論文 >  非晶矽薄膜與氧化鋁薄膜對單晶矽基板雙層鈍化之研究

Please use this identifier to cite or link to this item: http://nchuir.lib.nchu.edu.tw/handle/309270000/152796

標題: 非晶矽薄膜與氧化鋁薄膜對單晶矽基板雙層鈍化之研究
The Study of Double Layer (a-Si:H/Al2O3)Passivation On Crystalline Silicon Wafer
作者: 賴彥名
Lai, Yen-Ming
Contributors: 貢中元
關鍵字: 鈍化;退火;載子生命週期;非晶矽;氧化鋁
日期: 2012
Issue Date: 2013-11-18 11:22:43 (UTC+8)
Publisher: 光電工程研究所
摘要: 本論文是研究可應用於HIT太陽能電池的雙層鈍化結構(氧化鋁及非晶矽薄膜),實驗使用品質較差的p-type雙拋單晶矽晶圓(生命週期約10 μs左右),結果分下列兩部分探討。

第一部分為找出最佳鈍化效果的非晶矽薄膜製作參數。用電漿輔助化學氣相沉積系統沉積非晶矽薄膜,改變不同氫稀釋比,不同的薄膜厚度,不同的退火溫度和不同的退火形式,探討非晶矽薄膜內部的氫原子鍵結變化對鈍化的影響。實驗使用最佳的製程參數,沉積厚度20 nm的非晶矽薄膜,在退火溫度250~300℃下,會呈現最好的效果,載子生命週期約從10 μs提升至55 μs左右。

第二部分是在最佳化的非晶矽薄膜上沉積氧化鋁薄膜,利用其場效鈍化製作雙層鈍化層。使用原子沉積系統沉積單層厚度20 nm的氧化鋁薄膜,經傳統爐管退火400~500℃載子生命週期達到最高值,有10倍顯著的提升。而氧化鋁薄膜加上非晶矽薄膜雙層鈍化結構,在400~500℃載子生命週期沒有顯著的提升,是因為非晶矽薄膜厚度太厚,弱化了氧化鋁薄膜負電場的寬度,場效鈍化的效果消失,所觀察到的雙層鈍化效果還是來自於非晶矽薄膜的表面鈍化。
Silicon is the most widely used material in photovoltaic (PV) industries for making solar panels that convert solar energy into electricity. As the wafer thickness reduction, the surface passivation technique becomes more important because surface defects dominate the minority carrier recombination rate and the solar cell efficiency.

In this thesis study, the Surface of Silicon was passivated by Al2O3 and amorphous silicon. as the bi-layer, it was expected that hydrogen bonding reduce interface states and negative field effect which yields maximum Passivation. The silicon used in this research is P-type double side polished Czochralski wafers with lifetime of around 10 μs. The experimental results can be separated into two parts :

The first part, by optimizing the thickness of amorphous Si layer (20 nm) and annealing condition (annealed at 250~300℃ 30 min. in N2), the minority carrier lifetime single crystalline wafer could be improved from 10 μs to 55 μs.

The second part, the 20 nm Al2O3 film deposited onto 10~20 nm amorphous silicon to form bi-layer and annealed around 400℃ to 500℃. Carrier lifetime of silicon wafer was not observed to have significant improve. We believed that the 20 nm amorphous silicon passivation is too thick to limit the effect of field passivation .
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