在交流訊號應力測試部分，將在閘極一端施加電壓應力並改變此電壓的頻率。當給的應力電壓為正極性時，不論頻率的大小，與非晶矽薄膜電晶體臨界電壓的退化現象並無直接關係，因為此時主要造成元件退化的機制為電子捕捉，電子堆積的速度比閘極提供的交流訊號快很多，因此不受到頻率大小的影響。當給的應力電壓為負極性時，臨界電壓的退化現象明顯受到頻率大小的影響，這是由於Ｐ型載子電洞，和N型重摻雜非晶矽(n+-a-Si)層之間的電阻非常大，而當閘極快速的電壓變化時，因此當閘極的應力電壓快速變化時，產生了RC 延遲效應所致。當我們固定振幅為39 V和頻率為10 Hz交流應力訊號，改變應力電壓的起始值時，透過回復效應的觀察，發現當應力電壓範圍在-10~29 V時，幾乎達到了電子捕捉和電洞捕捉機制的平衡點，但由於缺陷態產生機制同時作用下，使得元件之臨界電壓上升。
Amorphous silicon thin film transistors, although the carrier mobility and device stability were not as good as poly-Si thin film transistors, due to the development of longer maturity of the technology and the low cost, therewas still valuable exploration on the stability of these devices in the driving circuits. In this study, the symmetrical structures of amorphous silicon thin film transistors were used.
For direct current (DC) biased stress, when we applied a DC gate voltage stress, the insulating layer (SiNx) and channel layer would be subject to the carrier trapping and the defect states creation mechanisms, so that the threshold voltage was changed. If we provided a positive biased stress on the gate, the electrons in the channel layer were attracted by the positive voltage, and the major trapping carriers would be electrons. If we gave a negative biased stress, the main carriers would be holes, resulting in hole trapping mechanism. No matter what negative or positive biased stresses on the gate, the defect creation mechanism would always make the threshold voltage increase. When the carriers transported, some of the carriers would be trapped in the insulating and channel layers. Although few carriers might enter the insulating and the channel layers, but not trapped, they would be influenced by the trapped carriers with the same polar charge and backed to drain and source. This effect was called recovery effect. The mobility of a-Si TFTs was much smaller than that of polySi ones, therefore, it was more easy to observe this recovery effect in the stability test of a-Si TFTs. If the threshold voltage became smaller after recovering, it represented the electron trapping was the dominant degradation mechanism.. If the threshold voltage increased after recovering, it represented the hole trapping was the dominant degradation mechanism.
For the alternating current (AC) biased stress, we applied to the biased stress on the gate and changed the frequency of these AC signals. In the condition of the positive biased stress, regardless of the AC signals frequencies, the Vth instability of a-Si TFTs was not dependent on these frequencies, because the major degradation in the device was caused by electron trapping mechanism. The accumulating speed of electrons would be much faster than that of the applied AC signal, and therefore, the degradation was not subject to the changing of AC frequency. On the contrary, in the negative biased stress condition, the threshold voltage shift was significantly affected by the changing of AC frequency, resulting from the high resistivity between the junctions of the accumulating hole and n+-a-Si(i.e. source and drain) layers. When the pulse signals of negative gate voltage changed rapidly, there was a RC delay effect existing in hole trapping mechanism. When we fixed the signal amplitude of 39 V and a frequency of 10 Hz, and changed the lowest value of the biased pulse signals, the balanced point of the Vth degradation almost achieved for the condition of pulse signal in the range of -10~29 V, and the final increase of Vth is caused by the defect states creation mechanism.