English  |  正體中文  |  简体中文  |  Items with full text/Total items : 43312/67235
Visitors : 2077245      Online Users : 3
RC Version 5.0 © Powered By DSPACE, MIT. Enhanced by NTU/NCHU Library IR team.
National Chung Hsing University Institutional Repository - NCHUIR > 工學院 > 光電工程研究所 > 依資料類型分類 > 碩博士論文 >  非晶矽薄膜電晶體臨界電壓在直流及交流電壓應力下的回復效應及不穩定性研究

Please use this identifier to cite or link to this item: http://nchuir.lib.nchu.edu.tw/handle/309270000/152797

標題: 非晶矽薄膜電晶體臨界電壓在直流及交流電壓應力下的回復效應及不穩定性研究
Study on the Recovery Effect and Instability of Threshold Voltage of Amorphous Silicon TFTs under DC/AC Stresses
作者: 紀佑旻
Chi, Yeo-Ming
Contributors: 劉漢文
Han-Wen Liu
光電工程研究所
關鍵字: 非晶矽薄膜電晶體;臨界電壓;回復效應
Amorphous Silicon;Threshold Voltage;Recovery Effect
日期: 2013
Issue Date: 2013-11-18 11:22:46 (UTC+8)
Publisher: 光電工程研究所
摘要: 非晶矽薄膜電晶體,雖然載子遷移率及元件穩定性皆不如多晶矽薄膜電晶體,但由於發展較久技術成熟且成本較低,因此元件在驅動電路的穩定性,仍有我們再探討的價值。本論文所採用的元件結構是對稱式的非晶矽薄膜電晶體。

在直流偏壓應力測試部分,當在元件閘極施加一直流電壓應力時,絕緣層(SiNx)、通道層中和其介面,會受到載子捕捉機制及缺陷態產生機制的影響,使臨界電壓發生變化;若我們給的是正偏壓應力測試,通道層中的電子受到正偏壓的吸引,此時主要的傳輸載子為電子,產生的機制為電子捕捉,若給的是負偏壓應力測試,主要傳輸載子為電洞,產生的機制為電洞捕捉,但不論正負偏壓應力測試,皆存在缺陷態產生的機制,使得臨界電壓上升;而載子在傳輸的過程當中,會有部分載子被捕捉於絕緣層及通道層中,而另一部分雖有進入絕緣層及通道層卻未被捕捉,未被捕捉的載子,在受到捕捉載子的相同電性影響下回到汲極和源極,稱做回復效應。由於氫化非晶矽比起多晶矽的載子遷移率小了許多,因此此載子回復的過程更容易的被我們所觀察。若是回復之後臨界電壓變小,代表當時主要捕捉的載子為電子,而回復的載子也是電子,若回復之後臨界電壓上升,代表當時主要捕捉的載子為電洞,回復的載子也是電洞。

在交流訊號應力測試部分,將在閘極一端施加電壓應力並改變此電壓的頻率。當給的應力電壓為正極性時,不論頻率的大小,與非晶矽薄膜電晶體臨界電壓的退化現象並無直接關係,因為此時主要造成元件退化的機制為電子捕捉,電子堆積的速度比閘極提供的交流訊號快很多,因此不受到頻率大小的影響。當給的應力電壓為負極性時,臨界電壓的退化現象明顯受到頻率大小的影響,這是由於P型載子電洞,和N型重摻雜非晶矽(n+-a-Si)層之間的電阻非常大,而當閘極快速的電壓變化時,因此當閘極的應力電壓快速變化時,產生了RC 延遲效應所致。當我們固定振幅為39 V和頻率為10 Hz交流應力訊號,改變應力電壓的起始值時,透過回復效應的觀察,發現當應力電壓範圍在-10~29 V時,幾乎達到了電子捕捉和電洞捕捉機制的平衡點,但由於缺陷態產生機制同時作用下,使得元件之臨界電壓上升。
Amorphous silicon thin film transistors, although the carrier mobility and device stability were not as good as poly-Si thin film transistors, due to the development of longer maturity of the technology and the low cost, therewas still valuable exploration on the stability of these devices in the driving circuits. In this study, the symmetrical structures of amorphous silicon thin film transistors were used.
For direct current (DC) biased stress, when we applied a DC gate voltage stress, the insulating layer (SiNx) and channel layer would be subject to the carrier trapping and the defect states creation mechanisms, so that the threshold voltage was changed. If we provided a positive biased stress on the gate, the electrons in the channel layer were attracted by the positive voltage, and the major trapping carriers would be electrons. If we gave a negative biased stress, the main carriers would be holes, resulting in hole trapping mechanism. No matter what negative or positive biased stresses on the gate, the defect creation mechanism would always make the threshold voltage increase. When the carriers transported, some of the carriers would be trapped in the insulating and channel layers. Although few carriers might enter the insulating and the channel layers, but not trapped, they would be influenced by the trapped carriers with the same polar charge and backed to drain and source. This effect was called recovery effect. The mobility of a-Si TFTs was much smaller than that of polySi ones, therefore, it was more easy to observe this recovery effect in the stability test of a-Si TFTs. If the threshold voltage became smaller after recovering, it represented the electron trapping was the dominant degradation mechanism.. If the threshold voltage increased after recovering, it represented the hole trapping was the dominant degradation mechanism.
For the alternating current (AC) biased stress, we applied to the biased stress on the gate and changed the frequency of these AC signals. In the condition of the positive biased stress, regardless of the AC signals frequencies, the Vth instability of a-Si TFTs was not dependent on these frequencies, because the major degradation in the device was caused by electron trapping mechanism. The accumulating speed of electrons would be much faster than that of the applied AC signal, and therefore, the degradation was not subject to the changing of AC frequency. On the contrary, in the negative biased stress condition, the threshold voltage shift was significantly affected by the changing of AC frequency, resulting from the high resistivity between the junctions of the accumulating hole and n+-a-Si(i.e. source and drain) layers. When the pulse signals of negative gate voltage changed rapidly, there was a RC delay effect existing in hole trapping mechanism. When we fixed the signal amplitude of 39 V and a frequency of 10 Hz, and changed the lowest value of the biased pulse signals, the balanced point of the Vth degradation almost achieved for the condition of pulse signal in the range of -10~29 V, and the final increase of Vth is caused by the defect states creation mechanism.
Appears in Collections:[依資料類型分類] 碩博士論文

Files in This Item:

File SizeFormat
index.html0KbHTML162View/Open


 


學術資源

著作權聲明

本網站為收錄中興大學學術著作及學術產出,已積極向著作權人取得全文授權,並盡力防止侵害著作權人之權益。如仍發現本網站之數位內容有侵害著作權人權益情事者,請權利人通知本網站維護人員,將盡速為您處理。

本網站之數位內容為國立中興大學所收錄之機構典藏,無償提供學術研究與公眾教育等公益性使用。

聯絡網站維護人員:wyhuang@nchu.edu.tw,04-22840290 # 412。

DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU/NCHU Library IR team Copyright ©   - Feedback