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標題: 2.4GHz全數位頻率合成器
2.4GHz All Digital Frequency Synthesizer
作者: 呂淙安
Lu, Cong-An
Contributors: 楊清淵
電機工程學系所
關鍵字: 鎖相迴路;全數位鎖相迴路;頻率合成器;全數位頻率合成器
phase locked loop;all digital phase plocked loop;frequency synthesizer;all digital frequency synthesizer
日期: 2013
Issue Date: 2013-11-21 11:08:28 (UTC+8)
Publisher: 電機工程學系所
摘要: 在目前的無線通訊中,我們一直希望無線收發機能夠在很寬廣的頻率範圍下切換頻率。因此,為了能夠在每一個通訊系統的通道產生所需的載波,一個穩定且可任意切換頻率的頻率合成器是必須的。其中一個在CMOS技術製程底下實現頻率合成的方法為建置全數位頻率合成器。全數位的實現方式可以對製程、電壓、溫度變異以及基底雜訊有較高的容忍度。同時,全數位頻率合成器具有以下的優點,像是較小的佈局面積、較容易驗證的特性、較低的功率消耗。這篇論文主要的內容是在設計應用於ISM頻帶的CMOS射頻全數位整數型頻率合成器。
本篇論文介紹了數種的時間數位轉換器架構以及具有快速鎖定技巧的全數位鎖相迴路,並實現三個具有快速鎖定技巧的全數位頻率合成器。第一個架構主要是具有鎖頻迴路以及鎖相迴路的頻率合成器,其鎖頻迴路可以偵測頻率差,加快鎖定的時間,其製程是使用台積電0.18微米互補式金氧半導體製程,晶片面積為1.2mm ×1.19964 mm,輸出鎖定範圍為2.02GHz-2.25GHz,鎖相迴路的相位雜訊為-97.97dBc/ Hz,在操作電壓為1.8V下,消耗功率為75mW,鎖定時間最快為76us。第二個架構為具有鎖頻迴路以及相位差補償技巧電路的全數位頻率合成器,相位差補償技巧電路可以改善相位差快速累積的問題,因此能夠達到更快速的鎖定,其製程是使用台積電0.18微米互補式金氧半導體製程,晶片面積為1.4mm ×1.4mm,模擬結果的輸出鎖定範圍為2.08GHz-2.403GHz,鎖相迴路的相位雜訊為-108dBc/Hz,在操作電壓為1.8V下,消耗功率為50mW,鎖定時間最快為45us。第三個架構為具有三段時間數位轉換器和相位差補償技巧的全數位頻率合成器,時間數位轉換器能達到寬範圍且高解析度,其製程亦是使用台積電0.18微米互補式金氧半導體製程,晶片面積為1.2mm×1.196mm,其模擬結果輸出鎖定範圍為2.325GHz-2.485GHz,鎖相迴路的相位雜訊為-120 dBc/Hz,在操作電壓為1.8V下,消耗功率為55mW,鎖定時間最快為6us。
In modern wireless communication, transceivers are expected to switch over a wide range of frequencies. Hence , a stable and switchable frequency synthesizer is employed to generate the required carriers for each channel in communication system. One approach to realize frequency synthesis is to implement an all-digital frequency synthesizer in CMOS technology. All digital approach can have a high tolerance to against process-voltage-temperature (PVT) variation and substrate noise . It also have many advantages, including smaller layout area, ease of testability, and less power dissipation. In this thesis, a CMOS RF all digital integer-N frequency synthesizer for ISM band is designed.

The thesis introduces several time-to-digital converters and all-digital phase-locked-loops with fast locking techniques. The first topology is a dual-loop all digital frequency synthesizer with frequency locked loop (FLL) and phase locked loop. The FLL detects the frequency error, and it also speeds up locking time.It is fabricated in TSMC 0.18um CMOS process, and it can provide the output frequency locking range from 2.01 GHz to 2.25GHz. The phase noise of the all digital frequency synthesizer is -97.97dBc/Hz. When the output locking frequency is 2.25GHz, the locking time is 76us and the power dissipation is 75mW under 1.8V supply voltage. The second topology is a dual-loop all digital frequency synthesizer with frequency-locked-loop and phase error compensation technique . The phase error compensation technique can improve large phase error accumulation problem. Fabricated in TSMC0.18um process, it can provide the output frequency locking range from 2.08GHzGHz to 2.403GHzGHz. When the output locking frequency is 2.402GHz, the locking time is 45us us and the power dissipation is 50mW under 1.8V supply voltage. The third topology is an all digital frequency synthesizer with phase error compensation technique and three time-to-digital converters.The time-to-digital converter can achieves wide range and high resolution performance . Fabricated in TSMC0.18um process, it can provide the output frequency locking range from 2.325GHz to 2.485GHz. When the output locking frequency is 2.405GHz, the locking time is 6us and the power dissipation is 50mW under 1.8V supply voltage.
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