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標題: 高功率半導體元件構裝熱應力分析暨改善設計
Package-level Thermal Stress Analysis and Design Improvement of High Power Semiconductor Devices
作者: 涂文彬
Tu, Wen-Bin
Contributors: 林明澤
精密工程學系所
關鍵字: 電子構裝;高功率半導體元件;熱應力;翹曲;有限元素法;田口法
Electronics Packaging;High Power Semiconductor Devices;Thermal Stress;Warpage;Finite Element Method;Taguchi method
日期: 2013
Issue Date: 2013-11-21 11:19:15 (UTC+8)
Publisher: 精密工程學系所
摘要: 電子構裝的整體結構主要是由導線架/基板、IC晶片、晶片基板之間連接線/球/柱、銲錫與封膠所組成。不同的構裝材料存在著不同的材料特性,因此在封膠製程中,各結構材料之間容易因熱膨脹係數的不同而產生不均勻熱應力,導致構裝膠體的變形,尤其是高功率元件作動時會產生高熱而導致此變形加劇。
本論文研究目標為針對高功率半導體電子構裝元件進行熱應力分析及改善設計;我們利用三次元量測儀實際量測電子構裝產品的翹曲變形數值,比對有限元素分析所模擬出的翹曲量,當成模擬分析正確與否的主要參考。由模擬分析與實際量測平均值對照,我們發現其誤差率僅為2.2%,其結果顯示模擬結果與實驗值相比是可信賴的。
模擬結果進一步顯示,在高溫穩態環境下的構裝元件之最大熱應力值發生在晶片正面角落位置,判定原因是晶片與封膠的熱膨脹係數差異較大所導致。最後,我們利用田口法之品質直交表排出9組實驗,由各組實驗所得知的應力值大小轉換成因子反應趨勢表,並且從因子反應表中以望小特性分析得到最佳組合參數,再次重新設定模擬參數,驗證該組合參數在封膠過後產生的熱應力最小,藉此改善此高功率構裝元件的品質與可靠度。
總之,本研究發現構裝元件表面的微小翹曲並不會影響之後與PCB板的組裝,我們確信以有限元素法模擬搭配田口品質設計,能獲得最小熱應力構裝相關參數,此方法應可有效增加電子構裝元件的品質與可靠度。
The structure of electronics packaging is constituted by a copper lead-frame, chips, wires, solder and molding compound. The different constituent materials have different characteristics. Different CTE (Coefficient of Thermal Expansion) of the constituent materials cause package deformed and thermal stresses for high temperature of mold chase or for high power devices that generate high heat when working.
This study focuses on the analysis of thermal stresses and improvement plan for high power semiconductor devices. To compare the actual warpage readings of electronics packaging that measured by 3D measuring instrument and the warpage value that simulated by finite element method. Result of experiment found that the difference between the actual readings and the simulated value is 2.2% that is trustworthy, and predict the thermal stresses of original electronics packaging in stable high temperature by simulation.
The maximum stress happened on the topside corner of the chip due to the difference of CTE between chips and compound is bigger. Therefore, this study designed Taguchi’s method with 9 orthogonal arrays to improve thermal stresses of the packing devices by this method. Then get the value of thermal stress by orthogonal arrays of experiments converts to the trend table, and get the optimization parameter via the stress is smaller the Better(STB) in the factor reflects table. Set up the simulation parameter of optimization again, the FEM proves this is the best condition for minimum thermal stress.
This study found micro-warpage on device surface could not affect assembly with substrate. Moreover, to use Taguchi method and finite element method can analyze out a better condition of small stress and effective increase the reliability of packaging.
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