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National Chung Hsing University Institutional Repository - NCHUIR > 工學院 > 電機工程學系所 > 依資料類型分類 > 碩博士論文 >  電極電壓對靜電式晶圓座(ESC)晶圓釋放的影響研究

Please use this identifier to cite or link to this item: http://nchuir.lib.nchu.edu.tw/handle/309270000/154853

標題: 電極電壓對靜電式晶圓座(ESC)晶圓釋放的影響研究
Study on the Electrode Voltage to the Wafer-center Deviation During Wafer Release in an Electrostatic Chuck (ESC)
作者: 陳韋閔
Chen, Wei-Min
Contributors: 裴靜偉
Zingway Pei
電機工程學系所
關鍵字: 靜電式晶圓座;消除靜電電荷;晶圓釋放;晶圓位移
Electrostatic Chuck (ESC);discharge;wafer release;wafer shift
日期: 2013
Issue Date: 2013-11-21 11:21:20 (UTC+8)
Publisher: 電機工程學系所
摘要: 晶圓製造過程中,當晶圓進入製程腔體後,需要將晶圓固定在腔體內的載具上以開始製程。但一般機械式晶圓固定座(Mechanical Chuck)有邊緣損失及晶圓表面形變的問題,而後發展出的真空式晶圓固定座(Vacuum Chuck),又有在真空式腔體內無法有效確實吸附固定晶圓之問題。所以目前業界設備較常使用的晶圓箝制方式,當屬使用靜電式晶圓座(Electrostatic Chuck , ESC)來當作晶圓箝制在製程腔體內的載具。
但靜電式晶圓座在作用時,因為會施加一高電極電壓來使晶圓表面產生靜電電荷,來達到將晶圓以靜電吸附在腔體內晶圓載具上的作用,而在製程完畢,靜電式晶圓座電極電壓關閉後,雖然將晶圓靜置一段時間後,晶圓本身亦會因為電荷中和而將晶圓表面的靜電電荷消除,但在產線生產上,這並不符合生產成本中的產出量。所以在製程控制中,通常會需要能快速消除晶圓表面靜電電荷的方法。在製程結束後,施加一道和原本箝制電極電壓反相的電極電壓,來達到快速消除晶圓表面靜電電荷,即是業界較常採用的方法。
反相消除晶圓表面靜電電荷的電極電壓若設定不夠理想,會導致晶圓表面的靜電電荷消除不夠完全,這在全自動取片的生產製造設備中,容易造成取片異常,甚而導致破片,使得生產製造中的正常生產時間減少以及成本的提高。本文即就靜電式晶圓座在晶圓製程完成後,在消除晶圓表面靜電電荷步驟時,所施加的反相電極電壓的電壓大小和持續時間做一探討。發現加大電極電壓或延長電極電壓所施加的時間,均可得到較佳的消除晶圓表面靜電電荷的效果。
Among the wafer fabricate processing, while wafer enter process chamber, the wafer need fixed to the holder in chamber then begin to process. However, the normal Mechanical Chuck had problems of wafer edge losses and deformation of the wafer surface, after that time, the Vacuum Chuck developed, but it also had unable chuck wafer efficaciously and positively at vacuum chamber issue. So the method presently applied of wafer chuck in equipment by industry, usually using Electrostatic Chuck (ESC) to clamp wafer in the process chamber holder.
But while electrostatic chuck working, it will exert a high electrode voltage to let wafer surface full of electric charge, to make wafer fixed to wafer holder in the chamber by static force, when processing end, after electrostatic chuck off the electrode voltage, even though idle wafer quietly for letter time, the wafer still can scatter electric charge by electric charge neutralize, nevertheless, in production line, that does not accord throughput in the production costs. Therefore, in the processing control, usually need a method to scatter electric charge for faster in the wafer surface. While process end, acceded an electrode voltage with opposite clamp electrode voltage, to order scatter electric charge for faster, that method usually using by industry.
If the electrode discharge voltage framed not ideal, the electric charge on the wafer surface that will cause discharge not enough, in the process equipments for use full-automatic transfer, easy to cause wafer access abnormal, even cause wafer broken, reduce up time and raise production costs while wafer manufacturing. This paper discuss is, while wafer processing end, effects of an electrode discharge voltage and time for scatter electric charge for wafer surface on an electrostatic chuck. Detect raise discharge voltage or extend discharge time, both can cause better result for discharge electric charge on the wafer surface.
Appears in Collections:[依資料類型分類] 碩博士論文

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